The data throughput of modern mobile, consumer and automotive SoC devices has soared as high definition video content has become the norm and 5G wireless connectivity has become a reality. To meet these demands, the latest applications, media and virtual reality processors routinely contain multiple heterogeneous high performance SerDes (Serializer/Deserializer) ports, which must be tested at speed to meet the stringent quality standards of top-tier end customers. The benefits of SerDes ports over parallel busses are numerous, such as lower power consumption, lower EMI, improved immunity to transmission medium variability, and more efficient usage of PCB area and connector pins. With sophisticated equalization and error correction schemes, modern SerDes interfaces can achieve incredible chip-to-chip or board-to-board bandwidth on standard PCB material.
Once implemented and verified, a properly designed SerDes interface can provide a highly compelling value proposition for high bandwidth and low latency data transfer in a system. One major challenge to achieving that value proposition has been implementing high quality production test of these high performance interfaces at a reasonable cost. Due to the competing requirements of performance, scalability, flexibility and cost-effectiveness, ATE systems often struggle to meet the needs of leading-edge SerDes ports. Existing ATE solutions for production test of SerDes ports typically rely on multiplexing and “clocking up” the system’s base data rate to reach SerDes data rates. While this brute-force approach can achieve the desired data rate, there are several drawbacks. Often the use model is built upon a bus-based digital architecture, and is not a good fit for source-synchronous SerDes ports. Multiple stages of clock conditioning and data multiplexing result in a complex system that requires liquid cooling and has a limited number of transmit and receive channels per instrument, which in turn drives up the per-channel cost. To ameliorate the high channel costs, users typically create relay mux trees on their fixtures to share channels between ports and sites, reducing multi-site efficiency, driving up fixture complexity and cost, and slowing time to market.
Alternative approaches have been employed to work around the drawbacks of traditional ATE SerDes instruments. One approach is to build a “rack and stack” system that uses standalone bench instruments to handle the high speed SerDes test requirements. While the stimulus and measure performance of these instruments is undeniable, the cost, integration complexity and poor throughput can be deal-breakers. This approach may enable reasonable time to market for limited production volumes, but it does not scale to meet the volume and cost needs of large scale production. Another approach is to integrate FPGAs and specialized SerDes transceivers on the test fixture, to essentially create a SerDes test system on the fixture PCB. This approach can provide very compelling cost structure and throughput, but has some critical limitations. First, the integrity of the stimulus and measurements may be questionable and have limited traceability. Second, due to lack of proper development tools and environment, test program development and deployment can be prohibitively difficult. Finally, due to the focused nature of this type of solution, it typically will only be applicable to a narrow range of devices. Internal loopback or BIST within the device itself is also a common strategy. While this is useful for in-system test, it is not sufficient to meet the ppm requirements of leading end customers.
Coming up next: How Xcerra is meeting these challenges.